/*
 * system.h - SOPC Builder system and BSP software package information
 *
 * Machine generated for CPU 'cpu_0' in SOPC Builder design 'system_0'
 * SOPC Builder design path: C:/Projects/DE2_NetHub/system_0.sopcinfo
 *
 * Generated: Sat Sep 28 23:03:27 EDT 2024
 */

/*
 * DO NOT MODIFY THIS FILE
 *
 * Changing this file will have subtle consequences
 * which will almost certainly lead to a nonfunctioning
 * system. If you do modify this file, be aware that your
 * changes will be overwritten and lost when this file
 * is generated again.
 *
 * DO NOT MODIFY THIS FILE
 */

/*
 * License Agreement
 *
 * Copyright (c) 2008
 * Altera Corporation, San Jose, California, USA.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * This agreement shall be governed in all respects by the laws of the State
 * of California and by the laws of the United States of America.
 */

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/* Include definitions from linker script generator */
#include "linker.h"


/*
 * Audio_0 configuration
 *
 */

#define ALT_MODULE_CLASS_Audio_0 audio_dac_fifo
#define AUDIO_0_BASE 0x1b0215c
#define AUDIO_0_IRQ -1
#define AUDIO_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define AUDIO_0_NAME "/dev/Audio_0"
#define AUDIO_0_SPAN 4
#define AUDIO_0_TYPE "audio_dac_fifo"


/*
 * CPU configuration
 *
 */

#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys"
#define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x1b01020
#define ALT_CPU_CPU_FREQ 50000000u
#define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "tiny"
#define ALT_CPU_DATA_ADDR_WIDTH 0x19
#define ALT_CPU_DCACHE_LINE_SIZE 0
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_DCACHE_SIZE 0
#define ALT_CPU_EXCEPTION_ADDR 0x1a80020
#define ALT_CPU_FLUSHDA_SUPPORTED
#define ALT_CPU_FREQ 50000000
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 0
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
#define ALT_CPU_HAS_DEBUG_CORE 1
#define ALT_CPU_HAS_DEBUG_STUB
#define ALT_CPU_HAS_JMPI_INSTRUCTION
#define ALT_CPU_ICACHE_LINE_SIZE 0
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_ICACHE_SIZE 0
#define ALT_CPU_INST_ADDR_WIDTH 0x19
#define ALT_CPU_NAME "cpu_0"
#define ALT_CPU_RESET_ADDR 0x800000


/*
 * CPU configuration (with legacy prefix - don't use these anymore)
 *
 */

#define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x1b01020
#define NIOS2_CPU_FREQ 50000000u
#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "tiny"
#define NIOS2_DATA_ADDR_WIDTH 0x19
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_EXCEPTION_ADDR 0x1a80020
#define NIOS2_FLUSHDA_SUPPORTED
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 0
#define NIOS2_HARDWARE_MULX_PRESENT 0
#define NIOS2_HAS_DEBUG_CORE 1
#define NIOS2_HAS_DEBUG_STUB
#define NIOS2_HAS_JMPI_INSTRUCTION
#define NIOS2_ICACHE_LINE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
#define NIOS2_ICACHE_SIZE 0
#define NIOS2_INST_ADDR_WIDTH 0x19
#define NIOS2_RESET_ADDR 0x800000


/*
 * DM9000A configuration
 *
 */

#define ALT_MODULE_CLASS_DM9000A dm9000a
#define DM9000A_BASE 0x1b020e8
#define DM9000A_IRQ 6
#define DM9000A_IRQ_INTERRUPT_CONTROLLER_ID 0
#define DM9000A_NAME "/dev/DM9000A"
#define DM9000A_SPAN 8
#define DM9000A_TYPE "dm9000a"


/*
 * Define for each module class mastered by the CPU
 *
 */

#define __ALTERA_AVALON_EPCS_FLASH_CONTROLLER
#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_LCD_16207
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_PIO
#define __ALTERA_AVALON_SYSID_QSYS
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_UART
#define __ALTERA_GENERIC_TRISTATE_CONTROLLER
#define __ALTERA_NIOS2_QSYS
#define __AUDIO_DAC_FIFO
#define __BINARY_VGA_CONTROLLER
#define __DE2_DRV11J_SIGIN
#define __DM9000A
#define __ISP1362_IF
#define __SEG7_LUT_8
#define __SRAM_16BIT_512K


/*
 * GPIO_DATIN configuration
 *
 */

#define ALT_MODULE_CLASS_GPIO_DATIN altera_avalon_pio
#define GPIO_DATIN_BASE 0x1b02110
#define GPIO_DATIN_BIT_CLEARING_EDGE_REGISTER 0
#define GPIO_DATIN_BIT_MODIFYING_OUTPUT_REGISTER 0
#define GPIO_DATIN_CAPTURE 0
#define GPIO_DATIN_DATA_WIDTH 16
#define GPIO_DATIN_DO_TEST_BENCH_WIRING 0
#define GPIO_DATIN_DRIVEN_SIM_VALUE 0x0
#define GPIO_DATIN_EDGE_TYPE "NONE"
#define GPIO_DATIN_FREQ 50000000u
#define GPIO_DATIN_HAS_IN 1
#define GPIO_DATIN_HAS_OUT 0
#define GPIO_DATIN_HAS_TRI 0
#define GPIO_DATIN_IRQ -1
#define GPIO_DATIN_IRQ_INTERRUPT_CONTROLLER_ID -1
#define GPIO_DATIN_IRQ_TYPE "NONE"
#define GPIO_DATIN_NAME "/dev/GPIO_DATIN"
#define GPIO_DATIN_RESET_VALUE 0x0
#define GPIO_DATIN_SPAN 16
#define GPIO_DATIN_TYPE "altera_avalon_pio"


/*
 * GPIO_DATOUT configuration
 *
 */

#define ALT_MODULE_CLASS_GPIO_DATOUT altera_avalon_pio
#define GPIO_DATOUT_BASE 0x1b02120
#define GPIO_DATOUT_BIT_CLEARING_EDGE_REGISTER 0
#define GPIO_DATOUT_BIT_MODIFYING_OUTPUT_REGISTER 0
#define GPIO_DATOUT_CAPTURE 0
#define GPIO_DATOUT_DATA_WIDTH 16
#define GPIO_DATOUT_DO_TEST_BENCH_WIRING 0
#define GPIO_DATOUT_DRIVEN_SIM_VALUE 0x0
#define GPIO_DATOUT_EDGE_TYPE "NONE"
#define GPIO_DATOUT_FREQ 50000000u
#define GPIO_DATOUT_HAS_IN 0
#define GPIO_DATOUT_HAS_OUT 1
#define GPIO_DATOUT_HAS_TRI 0
#define GPIO_DATOUT_IRQ -1
#define GPIO_DATOUT_IRQ_INTERRUPT_CONTROLLER_ID -1
#define GPIO_DATOUT_IRQ_TYPE "NONE"
#define GPIO_DATOUT_NAME "/dev/GPIO_DATOUT"
#define GPIO_DATOUT_RESET_VALUE 0x0
#define GPIO_DATOUT_SPAN 16
#define GPIO_DATOUT_TYPE "altera_avalon_pio"


/*
 * GPIO_SIGOUT configuration
 *
 */

#define ALT_MODULE_CLASS_GPIO_SIGOUT altera_avalon_pio
#define GPIO_SIGOUT_BASE 0x1b02060
#define GPIO_SIGOUT_BIT_CLEARING_EDGE_REGISTER 0
#define GPIO_SIGOUT_BIT_MODIFYING_OUTPUT_REGISTER 1
#define GPIO_SIGOUT_CAPTURE 0
#define GPIO_SIGOUT_DATA_WIDTH 8
#define GPIO_SIGOUT_DO_TEST_BENCH_WIRING 0
#define GPIO_SIGOUT_DRIVEN_SIM_VALUE 0x0
#define GPIO_SIGOUT_EDGE_TYPE "NONE"
#define GPIO_SIGOUT_FREQ 50000000u
#define GPIO_SIGOUT_HAS_IN 0
#define GPIO_SIGOUT_HAS_OUT 1
#define GPIO_SIGOUT_HAS_TRI 0
#define GPIO_SIGOUT_IRQ -1
#define GPIO_SIGOUT_IRQ_INTERRUPT_CONTROLLER_ID -1
#define GPIO_SIGOUT_IRQ_TYPE "NONE"
#define GPIO_SIGOUT_NAME "/dev/GPIO_SIGOUT"
#define GPIO_SIGOUT_RESET_VALUE 0x0
#define GPIO_SIGOUT_SPAN 32
#define GPIO_SIGOUT_TYPE "altera_avalon_pio"


/*
 * ISP1362_dc configuration
 *
 */

#define ALT_MODULE_CLASS_ISP1362_dc ISP1362_IF
#define ISP1362_DC_BASE 0x1b02148
#define ISP1362_DC_IRQ 8
#define ISP1362_DC_IRQ_INTERRUPT_CONTROLLER_ID 0
#define ISP1362_DC_NAME "/dev/ISP1362_dc"
#define ISP1362_DC_SPAN 8
#define ISP1362_DC_TYPE "ISP1362_IF"


/*
 * ISP1362_hc configuration
 *
 */

#define ALT_MODULE_CLASS_ISP1362_hc ISP1362_IF
#define ISP1362_HC_BASE 0x1b02140
#define ISP1362_HC_IRQ 7
#define ISP1362_HC_IRQ_INTERRUPT_CONTROLLER_ID 0
#define ISP1362_HC_NAME "/dev/ISP1362_hc"
#define ISP1362_HC_SPAN 8
#define ISP1362_HC_TYPE "ISP1362_IF"


/*
 * SD_CLK configuration
 *
 */

#define ALT_MODULE_CLASS_SD_CLK altera_avalon_pio
#define SD_CLK_BASE 0x1b02100
#define SD_CLK_BIT_CLEARING_EDGE_REGISTER 0
#define SD_CLK_BIT_MODIFYING_OUTPUT_REGISTER 0
#define SD_CLK_CAPTURE 0
#define SD_CLK_DATA_WIDTH 1
#define SD_CLK_DO_TEST_BENCH_WIRING 0
#define SD_CLK_DRIVEN_SIM_VALUE 0x0
#define SD_CLK_EDGE_TYPE "NONE"
#define SD_CLK_FREQ 50000000u
#define SD_CLK_HAS_IN 0
#define SD_CLK_HAS_OUT 1
#define SD_CLK_HAS_TRI 0
#define SD_CLK_IRQ -1
#define SD_CLK_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SD_CLK_IRQ_TYPE "NONE"
#define SD_CLK_NAME "/dev/SD_CLK"
#define SD_CLK_RESET_VALUE 0x0
#define SD_CLK_SPAN 16
#define SD_CLK_TYPE "altera_avalon_pio"


/*
 * SD_CMD configuration
 *
 */

#define ALT_MODULE_CLASS_SD_CMD altera_avalon_pio
#define SD_CMD_BASE 0x1b020f0
#define SD_CMD_BIT_CLEARING_EDGE_REGISTER 0
#define SD_CMD_BIT_MODIFYING_OUTPUT_REGISTER 0
#define SD_CMD_CAPTURE 0
#define SD_CMD_DATA_WIDTH 1
#define SD_CMD_DO_TEST_BENCH_WIRING 0
#define SD_CMD_DRIVEN_SIM_VALUE 0x0
#define SD_CMD_EDGE_TYPE "NONE"
#define SD_CMD_FREQ 50000000u
#define SD_CMD_HAS_IN 0
#define SD_CMD_HAS_OUT 0
#define SD_CMD_HAS_TRI 1
#define SD_CMD_IRQ -1
#define SD_CMD_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SD_CMD_IRQ_TYPE "NONE"
#define SD_CMD_NAME "/dev/SD_CMD"
#define SD_CMD_RESET_VALUE 0x0
#define SD_CMD_SPAN 16
#define SD_CMD_TYPE "altera_avalon_pio"


/*
 * SD_DAT configuration
 *
 */

#define ALT_MODULE_CLASS_SD_DAT altera_avalon_pio
#define SD_DAT_BASE 0x1b020d0
#define SD_DAT_BIT_CLEARING_EDGE_REGISTER 0
#define SD_DAT_BIT_MODIFYING_OUTPUT_REGISTER 0
#define SD_DAT_CAPTURE 0
#define SD_DAT_DATA_WIDTH 1
#define SD_DAT_DO_TEST_BENCH_WIRING 0
#define SD_DAT_DRIVEN_SIM_VALUE 0x0
#define SD_DAT_EDGE_TYPE "NONE"
#define SD_DAT_FREQ 50000000u
#define SD_DAT_HAS_IN 0
#define SD_DAT_HAS_OUT 0
#define SD_DAT_HAS_TRI 1
#define SD_DAT_IRQ -1
#define SD_DAT_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SD_DAT_IRQ_TYPE "NONE"
#define SD_DAT_NAME "/dev/SD_DAT"
#define SD_DAT_RESET_VALUE 0x0
#define SD_DAT_SPAN 16
#define SD_DAT_TYPE "altera_avalon_pio"


/*
 * SEG7_Display configuration
 *
 */

#define ALT_MODULE_CLASS_SEG7_Display seg7_lut_8
#define SEG7_DISPLAY_BASE 0x1b02158
#define SEG7_DISPLAY_IRQ -1
#define SEG7_DISPLAY_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SEG7_DISPLAY_NAME "/dev/SEG7_Display"
#define SEG7_DISPLAY_SPAN 4
#define SEG7_DISPLAY_TYPE "seg7_lut_8"


/*
 * System configuration
 *
 */

#define ALT_DEVICE_FAMILY "Cyclone II"
#define ALT_IRQ_BASE NULL
#define ALT_LEGACY_INTERRUPT_API_PRESENT
#define ALT_LOG_PORT "/dev/uart_0"
#define ALT_LOG_PORT_BASE 0x1b02000
#define ALT_LOG_PORT_DEV uart_0
#define ALT_LOG_PORT_IS_UART
#define ALT_LOG_PORT_PRESENT
#define ALT_LOG_PORT_TYPE ALTERA_AVALON_UART
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/uart_0"
#define ALT_STDERR_BASE 0x1b02000
#define ALT_STDERR_DEV uart_0
#define ALT_STDERR_IS_UART
#define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_uart"
#define ALT_STDIN "/dev/uart_0"
#define ALT_STDIN_BASE 0x1b02000
#define ALT_STDIN_DEV uart_0
#define ALT_STDIN_IS_UART
#define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_uart"
#define ALT_STDOUT "/dev/uart_0"
#define ALT_STDOUT_BASE 0x1b02000
#define ALT_STDOUT_DEV uart_0
#define ALT_STDOUT_IS_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDOUT_TYPE "altera_avalon_uart"
#define ALT_SYSTEM_NAME "system_0"


/*
 * VGA_0 configuration
 *
 */

#define ALT_MODULE_CLASS_VGA_0 binary_vga_controller
#define VGA_0_BASE 0x1800000
#define VGA_0_IRQ -1
#define VGA_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define VGA_0_NAME "/dev/VGA_0"
#define VGA_0_SPAN 2097152
#define VGA_0_TYPE "binary_vga_controller"


/*
 * altera_iniche configuration
 *
 */

#define INCLUDE_TCP
#define INICHE_DEFAULT_IF "NOT_USED"
#define IP_FRAGMENTS


/*
 * button_pio configuration
 *
 */

#define ALT_MODULE_CLASS_button_pio altera_avalon_pio
#define BUTTON_PIO_BASE 0x1b020b0
#define BUTTON_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define BUTTON_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define BUTTON_PIO_CAPTURE 1
#define BUTTON_PIO_DATA_WIDTH 4
#define BUTTON_PIO_DO_TEST_BENCH_WIRING 0
#define BUTTON_PIO_DRIVEN_SIM_VALUE 0x0
#define BUTTON_PIO_EDGE_TYPE "FALLING"
#define BUTTON_PIO_FREQ 50000000u
#define BUTTON_PIO_HAS_IN 1
#define BUTTON_PIO_HAS_OUT 0
#define BUTTON_PIO_HAS_TRI 0
#define BUTTON_PIO_IRQ 5
#define BUTTON_PIO_IRQ_INTERRUPT_CONTROLLER_ID 0
#define BUTTON_PIO_IRQ_TYPE "EDGE"
#define BUTTON_PIO_NAME "/dev/button_pio"
#define BUTTON_PIO_RESET_VALUE 0x0
#define BUTTON_PIO_SPAN 16
#define BUTTON_PIO_TYPE "altera_avalon_pio"


/*
 * cfi_flash_0 configuration
 *
 */

#define ALT_MODULE_CLASS_cfi_flash_0 altera_generic_tristate_controller
#define CFI_FLASH_0_BASE 0x1400000
#define CFI_FLASH_0_HOLD_VALUE 40
#define CFI_FLASH_0_IRQ -1
#define CFI_FLASH_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define CFI_FLASH_0_NAME "/dev/cfi_flash_0"
#define CFI_FLASH_0_SETUP_VALUE 40
#define CFI_FLASH_0_SIZE 4194304u
#define CFI_FLASH_0_SPAN 4194304
#define CFI_FLASH_0_TIMING_UNITS "ns"
#define CFI_FLASH_0_TYPE "altera_generic_tristate_controller"
#define CFI_FLASH_0_WAIT_VALUE 160


/*
 * epcs_controller configuration
 *
 */

#define ALT_MODULE_CLASS_epcs_controller altera_avalon_epcs_flash_controller
#define EPCS_CONTROLLER_BASE 0x1b01800
#define EPCS_CONTROLLER_IRQ 0
#define EPCS_CONTROLLER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define EPCS_CONTROLLER_NAME "/dev/epcs_controller"
#define EPCS_CONTROLLER_REGISTER_OFFSET 512
#define EPCS_CONTROLLER_SPAN 2048
#define EPCS_CONTROLLER_TYPE "altera_avalon_epcs_flash_controller"


/*
 * gpio_sigin configuration
 *
 */

#define ALT_MODULE_CLASS_gpio_sigin DE2_DRV11J_SIGIN
#define GPIO_SIGIN_BASE 0x1b02130
#define GPIO_SIGIN_IRQ 9
#define GPIO_SIGIN_IRQ_INTERRUPT_CONTROLLER_ID 0
#define GPIO_SIGIN_NAME "/dev/gpio_sigin"
#define GPIO_SIGIN_SPAN 16
#define GPIO_SIGIN_TYPE "DE2_DRV11J_SIGIN"


/*
 * hal configuration
 *
 */

#define ALT_MAX_FD 32
#define ALT_SYS_CLK TIMER_0
#define ALT_TIMESTAMP_CLK none


/*
 * jtag_uart_0 configuration
 *
 */

#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
#define JTAG_UART_0_BASE 0x1b020e0
#define JTAG_UART_0_IRQ 1
#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
#define JTAG_UART_0_READ_DEPTH 64
#define JTAG_UART_0_READ_THRESHOLD 8
#define JTAG_UART_0_SPAN 8
#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_0_WRITE_DEPTH 64
#define JTAG_UART_0_WRITE_THRESHOLD 8


/*
 * lcd_16207_0 configuration
 *
 */

#define ALT_MODULE_CLASS_lcd_16207_0 altera_avalon_lcd_16207
#define LCD_16207_0_BASE 0x1b02080
#define LCD_16207_0_IRQ -1
#define LCD_16207_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LCD_16207_0_NAME "/dev/lcd_16207_0"
#define LCD_16207_0_SPAN 16
#define LCD_16207_0_TYPE "altera_avalon_lcd_16207"


/*
 * led_green configuration
 *
 */

#define ALT_MODULE_CLASS_led_green altera_avalon_pio
#define LED_GREEN_BASE 0x1b020a0
#define LED_GREEN_BIT_CLEARING_EDGE_REGISTER 0
#define LED_GREEN_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LED_GREEN_CAPTURE 0
#define LED_GREEN_DATA_WIDTH 9
#define LED_GREEN_DO_TEST_BENCH_WIRING 0
#define LED_GREEN_DRIVEN_SIM_VALUE 0x0
#define LED_GREEN_EDGE_TYPE "NONE"
#define LED_GREEN_FREQ 50000000u
#define LED_GREEN_HAS_IN 0
#define LED_GREEN_HAS_OUT 1
#define LED_GREEN_HAS_TRI 0
#define LED_GREEN_IRQ -1
#define LED_GREEN_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LED_GREEN_IRQ_TYPE "NONE"
#define LED_GREEN_NAME "/dev/led_green"
#define LED_GREEN_RESET_VALUE 0x0
#define LED_GREEN_SPAN 16
#define LED_GREEN_TYPE "altera_avalon_pio"


/*
 * led_red configuration
 *
 */

#define ALT_MODULE_CLASS_led_red altera_avalon_pio
#define LED_RED_BASE 0x1b02090
#define LED_RED_BIT_CLEARING_EDGE_REGISTER 0
#define LED_RED_BIT_MODIFYING_OUTPUT_REGISTER 0
#define LED_RED_CAPTURE 0
#define LED_RED_DATA_WIDTH 18
#define LED_RED_DO_TEST_BENCH_WIRING 0
#define LED_RED_DRIVEN_SIM_VALUE 0x0
#define LED_RED_EDGE_TYPE "NONE"
#define LED_RED_FREQ 50000000u
#define LED_RED_HAS_IN 0
#define LED_RED_HAS_OUT 1
#define LED_RED_HAS_TRI 0
#define LED_RED_IRQ -1
#define LED_RED_IRQ_INTERRUPT_CONTROLLER_ID -1
#define LED_RED_IRQ_TYPE "NONE"
#define LED_RED_NAME "/dev/led_red"
#define LED_RED_RESET_VALUE 0x0
#define LED_RED_SPAN 16
#define LED_RED_TYPE "altera_avalon_pio"


/*
 * sdram_0 configuration
 *
 */

#define ALT_MODULE_CLASS_sdram_0 altera_avalon_new_sdram_controller
#define SDRAM_0_BASE 0x800000
#define SDRAM_0_CAS_LATENCY 3
#define SDRAM_0_CONTENTS_INFO ""
#define SDRAM_0_INIT_NOP_DELAY 0.0
#define SDRAM_0_INIT_REFRESH_COMMANDS 2
#define SDRAM_0_IRQ -1
#define SDRAM_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SDRAM_0_IS_INITIALIZED 1
#define SDRAM_0_NAME "/dev/sdram_0"
#define SDRAM_0_POWERUP_DELAY 100.0
#define SDRAM_0_REFRESH_PERIOD 15.625
#define SDRAM_0_REGISTER_DATA_IN 1
#define SDRAM_0_SDRAM_ADDR_WIDTH 0x16
#define SDRAM_0_SDRAM_BANK_WIDTH 2
#define SDRAM_0_SDRAM_COL_WIDTH 8
#define SDRAM_0_SDRAM_DATA_WIDTH 16
#define SDRAM_0_SDRAM_NUM_BANKS 4
#define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_0_SDRAM_ROW_WIDTH 12
#define SDRAM_0_SHARED_DATA 0
#define SDRAM_0_SIM_MODEL_BASE 1
#define SDRAM_0_SPAN 8388608
#define SDRAM_0_STARVATION_INDICATOR 0
#define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_0_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_0_T_AC 5.5
#define SDRAM_0_T_MRD 3
#define SDRAM_0_T_RCD 20.0
#define SDRAM_0_T_RFC 70.0
#define SDRAM_0_T_RP 20.0
#define SDRAM_0_T_WR 14.0


/*
 * sram_0 configuration
 *
 */

#define ALT_MODULE_CLASS_sram_0 sram_16bit_512k
#define SRAM_0_BASE 0x1a80000
#define SRAM_0_IRQ -1
#define SRAM_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SRAM_0_NAME "/dev/sram_0"
#define SRAM_0_SPAN 524288
#define SRAM_0_TYPE "sram_16bit_512k"


/*
 * switch_pio configuration
 *
 */

#define ALT_MODULE_CLASS_switch_pio altera_avalon_pio
#define SWITCH_PIO_BASE 0x1b020c0
#define SWITCH_PIO_BIT_CLEARING_EDGE_REGISTER 0
#define SWITCH_PIO_BIT_MODIFYING_OUTPUT_REGISTER 0
#define SWITCH_PIO_CAPTURE 0
#define SWITCH_PIO_DATA_WIDTH 18
#define SWITCH_PIO_DO_TEST_BENCH_WIRING 0
#define SWITCH_PIO_DRIVEN_SIM_VALUE 0x0
#define SWITCH_PIO_EDGE_TYPE "NONE"
#define SWITCH_PIO_FREQ 50000000u
#define SWITCH_PIO_HAS_IN 1
#define SWITCH_PIO_HAS_OUT 0
#define SWITCH_PIO_HAS_TRI 0
#define SWITCH_PIO_IRQ -1
#define SWITCH_PIO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SWITCH_PIO_IRQ_TYPE "NONE"
#define SWITCH_PIO_NAME "/dev/switch_pio"
#define SWITCH_PIO_RESET_VALUE 0x0
#define SWITCH_PIO_SPAN 16
#define SWITCH_PIO_TYPE "altera_avalon_pio"


/*
 * sysii configuration
 *
 */

#define ALT_MODULE_CLASS_sysii altera_avalon_sysid_qsys
#define SYSII_BASE 0x1b02150
#define SYSII_ID 0
#define SYSII_IRQ -1
#define SYSII_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SYSII_NAME "/dev/sysii"
#define SYSII_SPAN 8
#define SYSII_TIMESTAMP 1728756016
#define SYSII_TYPE "altera_avalon_sysid_qsys"


/*
 * timer_0 configuration
 *
 */

#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
#define TIMER_0_ALWAYS_RUN 0
#define TIMER_0_BASE 0x1b02020
#define TIMER_0_COUNTER_SIZE 32
#define TIMER_0_FIXED_PERIOD 0
#define TIMER_0_FREQ 50000000u
#define TIMER_0_IRQ 3
#define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_0_LOAD_VALUE 49999ull
#define TIMER_0_MULT 0.0010
#define TIMER_0_NAME "/dev/timer_0"
#define TIMER_0_PERIOD 1
#define TIMER_0_PERIOD_UNITS "ms"
#define TIMER_0_RESET_OUTPUT 0
#define TIMER_0_SNAPSHOT 1
#define TIMER_0_SPAN 32
#define TIMER_0_TICKS_PER_SEC 1000u
#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_0_TYPE "altera_avalon_timer"


/*
 * uart_0 configuration
 *
 */

#define ALT_MODULE_CLASS_uart_0 altera_avalon_uart
#define UART_0_BASE 0x1b02000
#define UART_0_BAUD 115200
#define UART_0_DATA_BITS 8
#define UART_0_FIXED_BAUD 1
#define UART_0_FREQ 50000000u
#define UART_0_IRQ 2
#define UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
#define UART_0_NAME "/dev/uart_0"
#define UART_0_PARITY 'N'
#define UART_0_SIM_CHAR_STREAM ""
#define UART_0_SIM_TRUE_BAUD 0
#define UART_0_SPAN 32
#define UART_0_STOP_BITS 1
#define UART_0_SYNC_REG_DEPTH 2
#define UART_0_TYPE "altera_avalon_uart"
#define UART_0_USE_CTS_RTS 0
#define UART_0_USE_EOP_REGISTER 0


/*
 * ucosii configuration
 *
 */

#define OS_ARG_CHK_EN 1
#define OS_CPU_HOOKS_EN 1
#define OS_DEBUG_EN 1
#define OS_EVENT_NAME_SIZE 32
#define OS_FLAGS_NBITS 16
#define OS_FLAG_ACCEPT_EN 1
#define OS_FLAG_DEL_EN 1
#define OS_FLAG_EN 1
#define OS_FLAG_NAME_SIZE 32
#define OS_FLAG_QUERY_EN 1
#define OS_FLAG_WAIT_CLR_EN 1
#define OS_LOWEST_PRIO 20
#define OS_MAX_EVENTS 60
#define OS_MAX_FLAGS 20
#define OS_MAX_MEM_PART 60
#define OS_MAX_QS 20
#define OS_MAX_TASKS 10
#define OS_MBOX_ACCEPT_EN 1
#define OS_MBOX_DEL_EN 1
#define OS_MBOX_EN 1
#define OS_MBOX_POST_EN 1
#define OS_MBOX_POST_OPT_EN 1
#define OS_MBOX_QUERY_EN 1
#define OS_MEM_EN 1
#define OS_MEM_NAME_SIZE 32
#define OS_MEM_QUERY_EN 1
#define OS_MUTEX_ACCEPT_EN 1
#define OS_MUTEX_DEL_EN 1
#define OS_MUTEX_EN 1
#define OS_MUTEX_QUERY_EN 1
#define OS_Q_ACCEPT_EN 1
#define OS_Q_DEL_EN 1
#define OS_Q_EN 1
#define OS_Q_FLUSH_EN 1
#define OS_Q_POST_EN 1
#define OS_Q_POST_FRONT_EN 1
#define OS_Q_POST_OPT_EN 1
#define OS_Q_QUERY_EN 1
#define OS_SCHED_LOCK_EN 1
#define OS_SEM_ACCEPT_EN 1
#define OS_SEM_DEL_EN 1
#define OS_SEM_EN 1
#define OS_SEM_QUERY_EN 1
#define OS_SEM_SET_EN 1
#define OS_TASK_CHANGE_PRIO_EN 1
#define OS_TASK_CREATE_EN 1
#define OS_TASK_CREATE_EXT_EN 1
#define OS_TASK_DEL_EN 1
#define OS_TASK_IDLE_STK_SIZE 512
#define OS_TASK_NAME_SIZE 32
#define OS_TASK_PROFILE_EN 1
#define OS_TASK_QUERY_EN 1
#define OS_TASK_STAT_EN 1
#define OS_TASK_STAT_STK_CHK_EN 1
#define OS_TASK_STAT_STK_SIZE 512
#define OS_TASK_SUSPEND_EN 1
#define OS_TASK_SW_HOOK_EN 1
#define OS_TASK_TMR_PRIO 0
#define OS_TASK_TMR_STK_SIZE 512
#define OS_THREAD_SAFE_NEWLIB 1
#define OS_TICKS_PER_SEC TIMER_0_TICKS_PER_SEC
#define OS_TICK_STEP_EN 1
#define OS_TIME_DLY_HMSM_EN 1
#define OS_TIME_DLY_RESUME_EN 1
#define OS_TIME_GET_SET_EN 1
#define OS_TIME_TICK_HOOK_EN 1
#define OS_TMR_CFG_MAX 16
#define OS_TMR_CFG_NAME_SIZE 16
#define OS_TMR_CFG_TICKS_PER_SEC 10
#define OS_TMR_CFG_WHEEL_SIZE 2
#define OS_TMR_EN 0

#endif /* __SYSTEM_H_ */
